PHASE 03SCHEMATIC

Think of the schematic as six small problems standing between a bare ESP32 module and a board you can plug in and flash. The board needs the right voltage, a steady supply, a defined way to boot, a USB port that negotiates power, something you can see, and a shield from the outside world. Each section below takes one of those problems and shows you the exact parts that solve it. Read them in order — they follow the power as it comes in at the USB connector and works its way to the chip. Every part has a refdes — U1, C5, R3 — the short label that ties its symbol, its BOM line, and its spot on the board together. You'll meet them in the tables under each section, and you can spin the 3D model of the headline parts as you go.

That something is **U2**, the RT9080. It's an LDO — short for low-dropout — which is just a voltage regulator that holds its output steady even when the input is only a little above it. Why not a simple voltage divider (two resistors)? Because a divider sags the moment the chip pulls current — and the ESP32's draw jumps every time its radio transmits. A regulator actively holds 3.3 V no matter the load. That's the whole point of a regulator. One thing to remember: the RT9080 needs a capacitor on its input and another on its output to stay stable — that's **C5** and **C6**, 1 µF each. The datasheet promises stability with 1 µF ceramic in and out, which is exactly what we gave it.

When the ESP32 switches its transistors millions of times a second, it grabs tiny gulps of current faster than the regulator across the board can possibly respond. Left unfed, the 3.3 V right at the chip's pins would dip on every gulp — and a microcontroller fed a dipping rail glitches or resets. The fix is a small capacitor parked right at each power pin: **C2, C3, and C7** (0.1 µF each). They hold a little reserve of charge and hand it over instantly when the chip asks, then refill between demands. **C1** (10 µF) plays the same game one size up — a bigger, slower reservoir for the whole rail, smoothing the larger swings the little caps don't cover. Together they're called bulk plus bypass.

The ESP32 checks two strapping pins the instant it wakes up: EN (chip-enable / reset) and GPIO0 (boot select). Both have to be at a definite level at that moment, so each gets a pull-up resistor — **R1** and **R2**, 10 kΩ — gently tying it to 3.3 V (logic high). EN high means the chip runs; GPIO0 high at reset means boot normally from flash. The two buttons override that resting level while you hold them. **SW1** pulls EN to ground to reset the chip; holding **SW2** (GPIO0 to ground) through a reset drops the chip into USB download mode so you can flash new firmware. The resistor sets the default; the button wins while it's pressed.

Your board announces itself as a consumer — a sink — by tying each CC pin to ground through a 5.1 kΩ resistor, called Rd. The host sees that exact resistance and only then switches VBUS on. There are two of them, **R3** and **R4**, because Type-C is reversible: whichever way the plug goes in, one of CC1/CC2 is the live one, so both need their own Rd. These are pull-down resistors (to ground) — the mirror image of the boot pull-ups you just met. And 5.1 kΩ isn't arbitrary; it's the value the USB-C spec assigns to a basic sink.

Give an LED more voltage than it wants and it pulls more and more current until it cooks itself. So you never connect one straight across a supply — you put a resistor in series with it to set the current. The math is just Ohm's law on the leftover voltage. The supply is 3.3 V; the red LED drops about 1.8 V across itself (its forward voltage, Vf), leaving 1.5 V across **R5**. With 470 Ω that's I = 1.5 V ÷ 470 Ω ≈ 3.2 mA — bright enough to see, easy on the GPIO driving it. **R5** and **R6** do this for LED1 (red, power) and LED2 (yellow, user).

It gets two guardians. **F1** is a resettable fuse (a PTC polyfuse) on VBUS: if something downstream pulls too much current, it heats up, its resistance shoots up, and it throttles the current down to a trickle — then, once it cools off, it returns to normal all by itself. **D1** is an ESD-protection array (the USBLC6-2) on the two data lines and VBUS. When a static spike arrives — thousands of volts off a fingertip — it clamps that spike to ground in a nanosecond with a clamping diode, before it can punch through the ESP32's delicate USB pins. It's deliberately a low-capacitance part, because USB data is fast and a bulky protector would smear the signal.

You've now reasoned out every part — so now you draw it. Start from the KiCad starter below: it's a ready-made project, with the symbol library plus every BOM part already dropped onto the sheet, spaced out but not yet wired. Your job isn't to find parts, it's to arrange them into a readable layout and wire them into the real circuit. A good schematic isn't just correct, it's readable: someone (including future-you) should be able to follow it at a glance. A few habits and one rules-check get you there.

Drag each part so the sheet reads left → right: inputs on the left, outputs on the right. Put power symbols (3V3, VBUS) at the top pointing up, and grounds at the bottom pointing down. Group parts by sub-circuit, the same way you just learned them — the USB-C front end together, the regulator together, the ESP32 and its caps together. And keep each decoupling capacitor right next to the pin it feeds, so the schematic mirrors how the part has to sit on the real board.

For anything that crosses the sheet — a power rail, a reset line — give the wire a net label instead of dragging a line all the way across: two wires that share a label are connected, and the drawing stays clean. Use power ports for 3V3 and GND so every part taps the rail by name. And remember that wires which merely cross aren't joined unless there's a junction dot — let KiCad drop those at real T-connections.

ERC reads your whole schematic and flags what's electrically wrong — a pin connected to nothing, two outputs fighting each other, a power rail that nothing drives. Run it, then work the list down to zero. The bar is the same one you'll meet again at DRC: clean, or every remaining flag is an exception you've marked and understood — not one you scrolled past.

1. Run ERC until it's clean — or every remaining flag is marked and understood.
2. Plot the schematic to PDF (File → Plot) for a readable copy, and keep the .kicad_sch source.
3. Attach the schematic as this stage's artifact — that's what the gate below checks.